This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Korean Application Serial No. 2001-23182 filed Apr. 28, 2001, the entire contents of which are incorporated by reference herein.
The present invention relates to semiconductor devices and methods for fabricating the same, more particularly, to high voltage devices and methods for fabricating the same that improves voltage-resistant characteristics when high voltage is applied to a gate electrode.
Generally, where an external system which employs a high voltage is controlled by an integrated circuit, the integrated circuit requires a device for controlling the high voltage. The device requires a structure having a high breakdown voltage.
In other words, for a drain or source of a transistor to which high voltage is directly applied, the punch-through voltage between the drain, source, and semiconductor substrate and the breakdown voltage between the drain, source, and well or substrate should be greater than the high voltage.
A double-diffused metal oxide semiconductor (DMOS) having a PN diode therein is generally used as a semiconductor device for high voltages. In this case, a drain region is formed as a double impurity diffused region so that the punch-through voltage and the breakdown voltage of the transistor become high while a PN diode is formed between the source and drain to prevent the device from being broken down by overvoltage when the transistor is turned off.
A known high voltage device and a method for fabricating the same will be described with reference to the accompanying drawings.
FIG. 1 is a sectional view illustrating a high voltage device known in the art, and FIG. 2 is a sectional view illustrating another high voltage device known in the art.
Examples of high voltage devices include a lateral diffused metal oxide semiconductor (LDMOS) transistor and a double diffused drain (DDD) MOS transistor.
FIG. 1 shows an LDMOS transistor. The LDMOS transistor includes an n-type semiconductor substrate 11, a p-type well 12, a drain region 13, a source region 14, a gate oxide film 15, a gate electrode 16, a drain contact 17, and a source contact 18. P-type well 12 is formed in a predetermined portion of semiconductor substrate 11. Drain region 13 is formed as an n-type heavily-doped impurity layer in one region within p-type well 12 at a predetermined depth. Source region 14 is formed as an n-type heavily-doped impurity layer in one region of semiconductor substrate 11 at a predetermined distance from p-type well 12. Gate oxide film 15 is formed having a first thickness on drain region 13, p-type well 12, and semiconductor substrate 11 adjacent to p-type well 12. Gate oxide film 15 is also formed having a second thickness greater than the first thickness on source region 14 and semiconductor substrate 11 adjacent to source region 14. Gate electrode 16 is formed on a predetermined region of gate oxide film 15 at a predetermined distance from source region 14 and overlaps drain region 13 and p-type well 12 adjacent to drain region 13 at an upper portion. Drain contact 17 and source contact 18 are in respective contact with drain region 13 and source region 14 through gate oxide film 15.
FIG. 2 shows a high voltage transistor having a DDD structure. The high voltage transistor having a DDD structure includes a p-type substrate 21, a gate oxide film 25, a gate electrode 26, an n-type drift region 22, an n-type heavily-doped drain region 23, an n-type heavily-doped source region 24, a drain contact 27, and a source contact 28. Gate oxide film 25 is formed on p-type substrate 21. Gate electrode 26 is formed in a predetermined portion on gate oxide film 25. N-type drift region 22 is formed in semiconductor substrate 21 at both sides below gate electrode 26 at a predetermined depth, partially overlapping gate electrode 26 at a lower portion of an edge of gate electrode 26. N-type heavily-doped drain region 23 is formed within drift region 22 at one side of gate electrode 26. N-type heavily-doped source region 24 is formed within drift region 22 at the other side of gate electrode 26. Drain contact 27 and source contact 28 are in respective contact with drain region 23 and source region 24 through gate oxide film 25.
In known high voltage devices, to improve voltage-resistant characteristics, the distance between the edge portion of the gate electrode and the heavily-doped source and drain regions, i.e., the traverse length of the drift region is increased. However, with increases in packing density of the semiconductor device, the drift region has a reduced length. This deteriorates voltage-resistant characteristics of the high voltage device.
Accordingly, the present invention is directed to high voltage devices and method for fabricating the same. The present invention provides a high voltage device and a method for fabricating the same that improves voltage-resistant characteristics and reduces the size of a device in order to improve packing density.
In accordance with the invention, a high voltage device includes a semiconductor substrate having first, second, and third regions, the first region having vertical sidewalls at both sides, and the second and third regions having a height higher than that of the first region at both sides of the first region. A channel region is formed within a surface of the substrate belonging to the first region including some of the vertical sidewalls. A first insulating film is formed on a surface of the first region including the vertical sidewalls. Buffer conductive films are formed to be adjacent to the sidewalls of the first region and isolated from each other. A second insulating film is formed between the buffer conductive films to have a recess portion. A third insulating film is formed on an entire surface including the buffer conductive films. A gate electrode, insulated from lower layers by the third insulating film to fill the recess portion, is formed to partially overlap the buffer conductive films. Drift regions respectively are formed in the second and third regions to have a first depth, and source and drain regions are formed in the second and third regions to have a second depth less than the first depth.
In another aspect of the present invention, a method for fabricating a high voltage device includes the steps of forming drift regions in a semiconductor substrate, forming source and drain ion injection regions within the drift regions, forming a trench greater than the drift regions in one region of the semiconductor substrate, forming a first insulating film on an entire surface including the trench, forming a first conductive film on the first insulating film, selectively removing the first conductive film to form buffer conductive films at both sides of the trench, forming a second insulating film having a predetermined thickness below the trench, forming a third insulating film on the entire surface including the buffer conductive films, forming a second conductive film on the third insulating film, and selectively removing the second conductive film and the third insulating film to form a gate electrode on the trench and the buffer conductive films adjacent to the trench.
Additional advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.